WHAT: The RISC-V Foundation, a non-profit corporation controlled by 235 member companies to drive a new era of processor innovation via the adoption and implementation of the free and open RISC-V ISA, announces the agenda for its “Getting Started with RISC-V” events across China. As part of this program, RISC-V members will host presentations and live demonstrations showcasing the ecosystem’s overall explosive growth and discuss the Foundation’s increasing footprint particularly within China and the greater APAC region. This event also offers an opportunity for attendees to speak with RISC-V experts and other local RISC-V enthusiasts about the increased commercial adoption and growing number of implementations.
WHERE: The Crowne Plaza Landmark in Shenzhen; the Sheraton Chengdu Lido Hotel in Chengdu; the Hyatt on the Bund; Alibaba in Hangzhou; the Bellagio in Shanghai; the Crowne Plaza Zhongguancun in Beijing.
WHEN: Monday, May 6; Wednesday, May 8; Monday, May 13; Tuesday, May 14; and Thursday, May 16
DETAILS: The RISC-V Foundation in collaboration with the Linux Foundation is hosting a series of free, one-day “Getting Started with RISC-V” events. These non-consecutive one-day seminars will feature 13 RISC-V Foundation members including Alibaba Group, Andes Technology, Codasip, GreenWaves Technologies, Nervos, Nuclei System, NXP, PerfXLab, SiFive, Syntacore, Tangram, UC TECH IP and UltraSoC.
Getting Started with RISC-V Agenda
Welcome and Check in
When: 8:30 a.m. – 9 a.m. GMT+8
Introduction to RISC-V
When: 9 a.m. – 9:20 a.m. GMT+8
Who: RISC-V Foundation
Nuclei RISC-V Solution Paves the Way to Your Application Defined Chip
When: 9:20 a.m. – 9:40 a.m. GMT+8
Who: Nuclei System
Pushing Data from the Edge to the Cloud with RISC-V Ecosystem
When: 9:40 a.m. – 10 a.m. GMT+8
Who: Alibaba Group
Productivity Tools for Automated Generation of RISC-V Processors
When: 10 a.m. – 10:20 a.m. GMT+8
Who: Codasip
Break
When: 10:20 a.m. – 10:50 a.m. GMT+8
How to Choose Your AIoT RISC-V Core? 如何選擇你的AIoT RISC-V核心?
When: 10:50 a.m. – 11:10 a.m. GMT+8
Who: Andes Technology
Perf-V: The Cost-Effective Development Board for RISC-V Community
When: 11:10 a.m. – 11:30 a.m. GMT+8
Who: PerfXLab
Enabling AIoT with RISC-V on a Battery for Years
When: 11:30 a.m. – 11:50 a.m. GMT+8
Who: GreenWaves Technologies
Lunch
When: 11:50 a.m. – 1 p.m. GMT+8
SCRx Family of the RISC-V Compatible Processor IP
When: 1 p.m. – 1:20 p.m. GMT+8
Who: Syntacore
RISC-V Enters the Mainstream – Next Steps for the Ecosystem
When: 1:20 p.m. – 1:40 p.m. GMT+8
Who: UltraSoC
TG403: a High-Performance Secure RISC-V Based MCU for Embedded Applications
When: 1:40 p.m. – 2 p.m. GMT+8
Who: Tangram
Break
When: 2 p.m. – 2:30 p.m. GMT+8
Expanding RISC-V Ecosystem for China Adoption 扩展RISC-V生态系统，助力中国市场
When: 2:30 p.m. – 2:50 p.m. GMT+8
Who: NXP
Innovation Unleashed: Solutions and Silicon Enabling the Intelligent Edge and Linux
When: 2:50 p.m. – 3:10 p.m. GMT+8
Who: SiFive
CKB-VM: a Blockchain Focused, General-Purpose Applicable Software Sandbox System Based on RISC-V
When: 3:10 p.m. – 3:30 p.m. GMT+8*
Who: Nervos
Innovation Thrust
When: 3:30 p.m. – 3:50 p.m. GMT+8*
Who: UC TECH IP
*Please note, the Nervos and UC TECH IP presentations will only take place at the Hangzhou event.
Each event is admission free, see below to register.
Shenzhen: May 6 at the Crowne Plaza Landmark Shenzhen – please register here.
Chengdu: May 8 at the Sheraton Chengdu Lido Hotel – please register here.
Shanghai: May 13 at the Hyatt on the Bund – please register here.
Hangzhou: May 14 at the Alibaba – please register here.
Beijing: May 16 at the Crowne Plaza Zhongguancun – please register here.
To learn more about the RISC-V China Roadshow, please visit: https://www.lfasiallc.com/events/risc-v-china-roadshow-2019/
For press interested in attending and scheduling meetings with the RISC-V Foundation and member companies, please email: [email protected].
To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.